The present invention relates to semiconductor integrated circuit devices and more particularly to a technique which is effective for its application to a semiconductor integrated circuit device having at least two of a MISFET (metal insulator semiconductor field effect transistor), a bipolar transistor and a resistor.
With the circuit configuration highly integrated, the MOSFET (metal oxide semiconductor field effect transistor) included in a semiconductor integrated circuit device tends to be miniaturized. The tendency of the MOSFET to miniaturization urges a reduction in gate electrode length which leads to an increase in the wiring conductor resistance, shallow junctions of source/drain regions which leads to an increase in the source/drain resistance and small areas of the source/drain regions which leads to an increase in their contact resistances, thus preventing high-speed operation. Under the circumstances, with the aim of increasing the operation speed, a salicide (self aligned silicide) technique for formation of silicide layers on the upper surfaces of the gate electrode, source region and drain region has been employed. According to the salicide technique, a silicide layer is formed in a self-aligned fashion with a side wall spacer (insulating film) covering the side surface of the gate electrode of the MOSFET.
On the other hand, as a semiconductor integrated circuit device optimized for high integration, high speed and low power consumption, a semiconductor integrated circuit device having complementary MOSFET's (CMOS's) and an npn-type bipolar transistor has been developed. This type of semiconductor integrated circuit device uses the salicide technique with a view of further increasing the operation speed as described in, for example, IEDM, Technical Digest, 1987, pp.841-843. According to the salicide technique for the semiconductor integrated circuit device, the side surfaces of the gate electrodes of the complementary MOSFET's and the side surface of the emitter electrode of the npn-type bipolar transistor are covered with side wall spacers, a refractory metal film (for example, titanium film) is deposited on a whole surface of substrate including the upper surfaces of the gate electrode, source region, drain region, emitter electrode and extrinsic base region (base contact region) and thereafter the resulting structure is heat treated to form silicide layers on the upper surfaces of the gate electrode, source region, drain region, emitter electrode and extrinsic base region at a time.
JP-A-4-328833 (laid open on Nov. 17, 1992) discloses that in fabrication of a semiconductor integrated circuit device having a bipolar transistor, an emitter electrode is formed using a cap insulating film formed over the emitter electrode as a mask and an external base electrode is formed in a self-aligned fashion with the emitter electrode.
JP-A-63-244870 (laid open on Oct. 12, 1988) discloses that in fabrication of a semiconductor device having a MOS transistor and a bipolar transistor, a metal silicide layer is used for formation of specified one of electrodes of the transistor.
JP-A-3-48459 (laid open on Mar. 1, 1991) discloses that in fabrication of a semiconductor device having a MOS transistor and a bipolar transistor, side wall spacers for the MOS transistor and bipolar transistor are formed at a time.